1. Field of the Invention
The present invention relates to an auto-calibration method for a delay circuit, and more particularly to a method for dynamically calibrating the delay time of a circuit according to variations in surrounding conditions.
2. Description of the Related Art
Numerous electronic apparatuses employ only one clock signal to synchronize operations between various devices. For example, an electronic apparatus equipped with DRAMs synchronizes the clock time of output signals from DRAMs with that of its system. Consequentially, the clock signals generated from the system control the DRAMs and other active devices together, and synchronous operation and manipulation exist between them.
Because of the occurrence of clock skew, the synchronicity of the operation between the DRAMs and system clock generator is degraded. The clock skew is a delay phenomenon in a general circuit, and is resulted from the delay effect of a clock buffer circuit and a driving circuit or that of a resistance-inductance circuit.
FIG. 1 is a conventional waveform diagram of output data signals from a DDR (double data rate) DRAM. The timing of output data signals is enabled to be on active duty by the rising edge or falling edge of CK and CK#, which are two clock signals opposite in phase. DQ0-DQ7 represent data signals transmitted by data buses. The transmitting paths for these data signals are all different, hence signal skew exist therebetween. That is, the start of the available interval of the data signal DQ0 is the earliest one, and that of the data signal DQ7 is the latest one. By contrast, the end of the available interval of the data signal DQ0 is also the earliest one, and that of the data signal DQ7 is the latest one. Referring to FIG. 1, a data strobe signal DQS is designated as a sampling reference signal of the data signal.
As shown in FIG. 1, tHP is a half period of the clock signal CK; tDQSQ is the interval from the positive edge or the negative edge of the data strobe signal DQS to the end of the available interval on the data signal DQ0; tQH is the interval from the positive edge or the negative edge of the data strobe signal DQS to the end of the available interval on the data signal DQ7; the overlap between the available intervals of DQ0-DQ7 is a data valid window (DVW).
For the sake of accuracy and stability on data access, the positive edge or the negative edge of the data strobe signal DQS is preferably postponed to the center of the data valid window, and therefore a delay circuit 20 capable of adjusting delay time is put forth to satisfy the aforesaid preferable requirement. As shown in FIG. 2, the delay circuit 20 selects one of the delay chains 21-24 as the best delay path through a multiplexer 26 enabled to be on active duty by a tester 25 during the testing stage of an electronic apparatus. After the delay interval between the input terminal and output terminal is tuned to a default value, the delay time is constant, not variable.
Several disadvantages exist in the conventional way of tuning delay time and are to be overcome; for example, the best delay path is necessarily determined before the electronic apparatus with the delay circuit is used, and consequentially dynamical adjustment, depending on practical conditions in use, is unavailable. That is, the adjustment of delay time is not flexibly available under surrounding temperature increase or slice level shift. On the other hand, the best delay paths of all the devices need to be previously selected during their testing stages, hence the cost and cycle time expended in the manufacturing and testing are increased. In conclusion, such devices are not suitable for mass production.
The data valid window of a PC 133 DDR SDRAM module requires a minimum interval not less than 2.625 nsecs. It is necessary to consider skew time (around 0.513 nsec) resulted from the various characteristics of the print circuit board during the minimum data valid window, the setup and hold time (around 0.6 nsec) of the controller, and the strobe placement uncertainty (around 0.4 nsec) of the data strobe signal DQS. Therefore, the residual margin time is merely 0.1 nsec. Because the variation in the strobe placement uncertainty of the data strobe signal DQS can be doubled when surrounding temperature varies from case to case, errors occur frequently in data access.
In summary, a method for dynamically calibrating a delay circuit according to surrounding conditions is an urgent demand for the IC market so that the problems occurring in the high-speed data transmission and access of electronic devices can be resolved.